
Obj/FWlib_apt32f172_gpio.o:     file format elf32-csky-little


Disassembly of section .text:

00000000 <GPIO_DeInit>:
//IO RESET CLEAR ALL REGISTER
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/  
void GPIO_DeInit(void)
{
   0:	14c2      	push      	r4-r5
    GPIOA0->CONLR = GPIO_RESET_VALUE;                     
   2:	116b      	lrw      	r3, 0	// ac <GPIO_DeInit+0xac>
    GPIOA1->CONHR = GPIO_RESET_VALUE;
    GPIOB0->CONLR = GPIO_RESET_VALUE;                     
    GPIOB0->CONHR = GPIO_RESET_VALUE;
	GPIOC0->CONLR = GPIO_RESET_VALUE;                     
    GPIOC0->CONHR = GPIO_RESET_VALUE;
	GPIOD0->CONLR = GPIO_RESET_VALUE;                     
   4:	3500      	movi      	r5, 0
    GPIOA0->CONLR = GPIO_RESET_VALUE;                     
   6:	9380      	ld.w      	r4, (r3, 0)
   8:	3300      	movi      	r3, 0
   a:	b460      	st.w      	r3, (r4, 0)
    GPIOA0->CONHR = GPIO_RESET_VALUE;
   c:	b461      	st.w      	r3, (r4, 0x4)
	GPIOA1->CONLR = GPIO_RESET_VALUE;                     
   e:	1169      	lrw      	r3, 0	// b0 <GPIO_DeInit+0xb0>
  10:	9300      	ld.w      	r0, (r3, 0)
  12:	3300      	movi      	r3, 0
  14:	b060      	st.w      	r3, (r0, 0)
    GPIOA1->CONHR = GPIO_RESET_VALUE;
  16:	b061      	st.w      	r3, (r0, 0x4)
    GPIOB0->CONLR = GPIO_RESET_VALUE;                     
  18:	1167      	lrw      	r3, 0	// b4 <GPIO_DeInit+0xb4>
  1a:	9320      	ld.w      	r1, (r3, 0)
  1c:	3300      	movi      	r3, 0
  1e:	b160      	st.w      	r3, (r1, 0)
    GPIOB0->CONHR = GPIO_RESET_VALUE;
  20:	b161      	st.w      	r3, (r1, 0x4)
	GPIOC0->CONLR = GPIO_RESET_VALUE;                     
  22:	1166      	lrw      	r3, 0	// b8 <GPIO_DeInit+0xb8>
  24:	9340      	ld.w      	r2, (r3, 0)
  26:	3300      	movi      	r3, 0
  28:	b260      	st.w      	r3, (r2, 0)
    GPIOC0->CONHR = GPIO_RESET_VALUE;
  2a:	b261      	st.w      	r3, (r2, 0x4)
	GPIOD0->CONLR = GPIO_RESET_VALUE;                     
  2c:	1164      	lrw      	r3, 0	// bc <GPIO_DeInit+0xbc>
  2e:	9360      	ld.w      	r3, (r3, 0)
  30:	b3a0      	st.w      	r5, (r3, 0)
    GPIOD0->CONHR = GPIO_RESET_VALUE;
  32:	b3a1      	st.w      	r5, (r3, 0x4)
    GPIOA0->WODR  = GPIO_RESET_VALUE; 
  34:	b4a2      	st.w      	r5, (r4, 0x8)
	GPIOA1->WODR  = GPIO_RESET_VALUE; 
  36:	b0a2      	st.w      	r5, (r0, 0x8)
    GPIOB0->WODR  = GPIO_RESET_VALUE;
  38:	b1a2      	st.w      	r5, (r1, 0x8)
	GPIOC0->WODR  = GPIO_RESET_VALUE;
  3a:	b2a2      	st.w      	r5, (r2, 0x8)
	GPIOD0->WODR  = GPIO_RESET_VALUE;
  3c:	b3a2      	st.w      	r5, (r3, 0x8)
    GPIOA0->SODR  = GPIO_RESET_VALUE; 
  3e:	b4a3      	st.w      	r5, (r4, 0xc)
	GPIOA1->SODR  = GPIO_RESET_VALUE; 
  40:	b0a3      	st.w      	r5, (r0, 0xc)
    GPIOB0->SODR  = GPIO_RESET_VALUE;
  42:	b1a3      	st.w      	r5, (r1, 0xc)
	GPIOC0->SODR  = GPIO_RESET_VALUE; 
  44:	b2a3      	st.w      	r5, (r2, 0xc)
	GPIOD0->SODR  = GPIO_RESET_VALUE; 
  46:	b3a3      	st.w      	r5, (r3, 0xc)
    GPIOA0->CODR  = GPIO_RESET_VALUE; 
  48:	b4a4      	st.w      	r5, (r4, 0x10)
	GPIOA1->CODR  = GPIO_RESET_VALUE; 
  4a:	b0a4      	st.w      	r5, (r0, 0x10)
    GPIOB0->CODR  = GPIO_RESET_VALUE;
  4c:	b1a4      	st.w      	r5, (r1, 0x10)
	GPIOC0->CODR  = GPIO_RESET_VALUE;
  4e:	b2a4      	st.w      	r5, (r2, 0x10)
	GPIOD0->CODR  = GPIO_RESET_VALUE;
  50:	b3a4      	st.w      	r5, (r3, 0x10)
    GPIOA0->PUDR  = GPIO_RESET_VALUE; 
  52:	b4a8      	st.w      	r5, (r4, 0x20)
	GPIOA1->PUDR  = GPIO_RESET_VALUE; 
  54:	b0a8      	st.w      	r5, (r0, 0x20)
    GPIOB0->PUDR  = GPIO_RESET_VALUE;
  56:	b1a8      	st.w      	r5, (r1, 0x20)
	GPIOC0->PUDR  = GPIO_RESET_VALUE;
  58:	b2a8      	st.w      	r5, (r2, 0x20)
	GPIOD0->PUDR  = GPIO_RESET_VALUE;
  5a:	b3a8      	st.w      	r5, (r3, 0x20)
    GPIOA0->DSCR  = GPIO_RESET_VALUE;
  5c:	b4a9      	st.w      	r5, (r4, 0x24)
	GPIOA1->DSCR  = GPIO_RESET_VALUE;
  5e:	b0a9      	st.w      	r5, (r0, 0x24)
    GPIOB0->DSCR  = GPIO_RESET_VALUE;
  60:	b1a9      	st.w      	r5, (r1, 0x24)
	GPIOC0->DSCR  = GPIO_RESET_VALUE;
  62:	b2a9      	st.w      	r5, (r2, 0x24)
	GPIOD0->DSCR  = GPIO_RESET_VALUE;
  64:	b3a9      	st.w      	r5, (r3, 0x24)
    GPIOA0->IECR  = GPIO_RESET_VALUE;
  66:	b4ab      	st.w      	r5, (r4, 0x2c)
	GPIOA1->IECR  = GPIO_RESET_VALUE;
  68:	b0ab      	st.w      	r5, (r0, 0x2c)
    GPIOB0->IECR  = GPIO_RESET_VALUE;
  6a:	b1ab      	st.w      	r5, (r1, 0x2c)
	GPIOC0->IECR  = GPIO_RESET_VALUE;
  6c:	b2ab      	st.w      	r5, (r2, 0x2c)
	GPIOD0->IECR  = GPIO_RESET_VALUE;
  6e:	b3ab      	st.w      	r5, (r3, 0x2c)
	GPIOA0->IEER  = GPIO_RESET_VALUE;
  70:	b4ac      	st.w      	r5, (r4, 0x30)
	GPIOA1->IEER  = GPIO_RESET_VALUE;
  72:	b0ac      	st.w      	r5, (r0, 0x30)
    GPIOB0->IEER  = GPIO_RESET_VALUE;
  74:	b1ac      	st.w      	r5, (r1, 0x30)
	GPIOC0->IEER  = GPIO_RESET_VALUE;
  76:	b2ac      	st.w      	r5, (r2, 0x30)
	GPIOD0->IEER  = GPIO_RESET_VALUE;
  78:	b3ac      	st.w      	r5, (r3, 0x30)
	GPIOA0->IEDR  = GPIO_RESET_VALUE;
  7a:	b4ad      	st.w      	r5, (r4, 0x34)
	GPIOA1->IEDR  = GPIO_RESET_VALUE;
  7c:	b0ad      	st.w      	r5, (r0, 0x34)
    GPIOB0->IEDR  = GPIO_RESET_VALUE;
  7e:	b1ad      	st.w      	r5, (r1, 0x34)
	GPIOC0->IEDR  = GPIO_RESET_VALUE;
  80:	b2ad      	st.w      	r5, (r2, 0x34)
	GPIOD0->IEDR  = GPIO_RESET_VALUE;
  82:	b3ad      	st.w      	r5, (r3, 0x34)
    GPIOA0->ODSR  = GPIO_RESET_VALUE;
  84:	b4a5      	st.w      	r5, (r4, 0x14)
	GPIOA1->ODSR  = GPIO_RESET_VALUE;
  86:	b0a5      	st.w      	r5, (r0, 0x14)
    GPIOB0->ODSR  = GPIO_RESET_VALUE;
  88:	b1a5      	st.w      	r5, (r1, 0x14)
	GPIOC0->ODSR  = GPIO_RESET_VALUE;
  8a:	b2a5      	st.w      	r5, (r2, 0x14)
	GPIOD0->ODSR  = GPIO_RESET_VALUE;
  8c:	b3a5      	st.w      	r5, (r3, 0x14)
    GPIOA0->OMCR  = GPIO_RESET_VALUE;
  8e:	b4aa      	st.w      	r5, (r4, 0x28)
	GPIOA1->OMCR  = GPIO_RESET_VALUE;
  90:	3400      	movi      	r4, 0
  92:	b08a      	st.w      	r4, (r0, 0x28)
    GPIOB0->OMCR  = GPIO_RESET_VALUE;
  94:	3000      	movi      	r0, 0
  96:	b10a      	st.w      	r0, (r1, 0x28)
	GPIOC0->OMCR  = GPIO_RESET_VALUE;
  98:	3100      	movi      	r1, 0
  9a:	b22a      	st.w      	r1, (r2, 0x28)
	GPIOD0->OMCR  = GPIO_RESET_VALUE;
  9c:	3200      	movi      	r2, 0
  9e:	b34a      	st.w      	r2, (r3, 0x28)
    EXIGRP->IGRPL = GPIO_RESET_VALUE;
  a0:	1068      	lrw      	r3, 0	// c0 <GPIO_DeInit+0xc0>
  a2:	9360      	ld.w      	r3, (r3, 0)
  a4:	b340      	st.w      	r2, (r3, 0)
	EXIGRP->IGRPH = GPIO_RESET_VALUE;
  a6:	b341      	st.w      	r2, (r3, 0x4)
}  
  a8:	1482      	pop      	r4-r5
	...

000000c4 <GPIO_Debug_IO_03_04>:
void GPIO_Debug_IO_03_04(void)
{
    GPIOA0->CONLR |= 0x00055000;
  c4:	1364      	lrw      	r3, 0	// 254 <GPIO_DriveStrength_DIS+0x4>
  c6:	32aa      	movi      	r2, 170
  c8:	9320      	ld.w      	r1, (r3, 0)
  ca:	9160      	ld.w      	r3, (r1, 0)
  cc:	424b      	lsli      	r2, r2, 11
  ce:	6cc8      	or      	r3, r2
  d0:	b160      	st.w      	r3, (r1, 0)
}
  d2:	783c      	rts

000000d4 <GPIO_Init>:
//byte:Lowbyte(PIN_0~7),Highbyte(PIN_8~15)
//Dir:0:output 1:input
//ReturnValue:NONE
/*************************************************************/  
void GPIO_Init(CSP_GPIO_T *GPIOx,U8_T PinNum,GPIO_Dir_TypeDef Dir)
{
  d4:	14d1      	push      	r4, r15
    uint32_t data_temp;
    uint8_t GPIO_Pin;
    if(PinNum<8)
  d6:	3907      	cmphsi      	r1, 8
{
  d8:	6d03      	mov      	r4, r0
    if(PinNum<8)
  da:	0830      	bt      	0x13a	// 13a <GPIO_Init+0x66>
    {
    switch (PinNum)
  dc:	5903      	subi      	r0, r1, 1
  de:	3806      	cmphsi      	r0, 7
  e0:	0827      	bt      	0x12e	// 12e <GPIO_Init+0x5a>
  e2:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
  e6:	1004      	.short	0x1004
  e8:	1d1a1613 	.long	0x1d1a1613
  ec:	0021      	.short	0x0021
    {
        case 0:data_temp=0xfffffff0;GPIO_Pin=0;break;
        case 1:data_temp=0xffffff0f;GPIO_Pin=4;break;
  ee:	3300      	movi      	r3, 0
  f0:	3104      	movi      	r1, 4
  f2:	2bf0      	subi      	r3, 241
        case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break;
        case 5:data_temp=0xff0fffff;GPIO_Pin=20;break;
        case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
        case 7:data_temp=0x0fffffff;GPIO_Pin=28;break;
    }
        if (Dir)
  f4:	3a40      	cmpnei      	r2, 0
        {
          (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<<GPIO_Pin;
  f6:	9440      	ld.w      	r2, (r4, 0)
  f8:	68c8      	and      	r3, r2
        if (Dir)
  fa:	0c1e      	bf      	0x136	// 136 <GPIO_Init+0x62>
          (GPIOx)->CONLR =((GPIOx)->CONLR & data_temp) | 1<<GPIO_Pin;
  fc:	3201      	movi      	r2, 1
        }
        else
        {
         (GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2<<GPIO_Pin; 
  fe:	7084      	lsl      	r2, r1
 100:	6cc8      	or      	r3, r2
 102:	b460      	st.w      	r3, (r4, 0)
        else
        {
         (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;    
        }
    }
}
 104:	1491      	pop      	r4, r15
        case 2:data_temp=0xfffff0ff;GPIO_Pin=8;break;
 106:	3108      	movi      	r1, 8
 108:	1274      	lrw      	r3, 0xfffff0ff	// 258 <GPIO_DriveStrength_DIS+0x8>
 10a:	07f5      	br      	0xf4	// f4 <GPIO_Init+0x20>
        case 3:data_temp=0xffff0fff;GPIO_Pin=12;break;
 10c:	310c      	movi      	r1, 12
 10e:	1274      	lrw      	r3, 0xffff0fff	// 25c <GPIO_DriveStrength_DIS+0xc>
 110:	07f2      	br      	0xf4	// f4 <GPIO_Init+0x20>
        case 4:data_temp=0xfff0ffff;GPIO_Pin=16;break;
 112:	3110      	movi      	r1, 16
 114:	1273      	lrw      	r3, 0xfff10000	// 260 <GPIO_DriveStrength_DIS+0x10>
        case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
 116:	2b00      	subi      	r3, 1
 118:	07ee      	br      	0xf4	// f4 <GPIO_Init+0x20>
        case 5:data_temp=0xff0fffff;GPIO_Pin=20;break;
 11a:	3114      	movi      	r1, 20
 11c:	1272      	lrw      	r3, 0xff100000	// 264 <GPIO_DriveStrength_DIS+0x14>
 11e:	07fc      	br      	0x116	// 116 <GPIO_Init+0x42>
        case 6:data_temp=0xf0ffffff;GPIO_Pin=24;break;
 120:	33f1      	movi      	r3, 241
 122:	3118      	movi      	r1, 24
 124:	4378      	lsli      	r3, r3, 24
 126:	07f8      	br      	0x116	// 116 <GPIO_Init+0x42>
        case 7:data_temp=0x0fffffff;GPIO_Pin=28;break;
 128:	311c      	movi      	r1, 28
 12a:	1270      	lrw      	r3, 0xfffffff	// 268 <GPIO_DriveStrength_DIS+0x18>
 12c:	07e4      	br      	0xf4	// f4 <GPIO_Init+0x20>
        case 0:data_temp=0xfffffff0;GPIO_Pin=0;break;
 12e:	3300      	movi      	r3, 0
 130:	3100      	movi      	r1, 0
 132:	2b0f      	subi      	r3, 16
 134:	07e0      	br      	0xf4	// f4 <GPIO_Init+0x20>
         (GPIOx)->CONLR = ((GPIOx)->CONLR & data_temp) | 2<<GPIO_Pin; 
 136:	3202      	movi      	r2, 2
 138:	07e3      	br      	0xfe	// fe <GPIO_Init+0x2a>
    else if (PinNum<16)
 13a:	390f      	cmphsi      	r1, 16
 13c:	0be4      	bt      	0x104	// 104 <GPIO_Init+0x30>
        switch (PinNum)
 13e:	2908      	subi      	r1, 9
 140:	3906      	cmphsi      	r1, 7
 142:	6c07      	mov      	r0, r1
 144:	0827      	bt      	0x192	// 192 <GPIO_Init+0xbe>
 146:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
 14a:	1004      	.short	0x1004
 14c:	1d1a1613 	.long	0x1d1a1613
 150:	0021      	.short	0x0021
        case 9:data_temp=0xffffff0f;GPIO_Pin=4;break;
 152:	3300      	movi      	r3, 0
 154:	3104      	movi      	r1, 4
 156:	2bf0      	subi      	r3, 241
      if (Dir)
 158:	3a40      	cmpnei      	r2, 0
        (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<<GPIO_Pin;  
 15a:	9441      	ld.w      	r2, (r4, 0x4)
 15c:	68c8      	and      	r3, r2
      if (Dir)
 15e:	0c1e      	bf      	0x19a	// 19a <GPIO_Init+0xc6>
        (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 1<<GPIO_Pin;  
 160:	3201      	movi      	r2, 1
         (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;    
 162:	7084      	lsl      	r2, r1
 164:	6cc8      	or      	r3, r2
 166:	b461      	st.w      	r3, (r4, 0x4)
}
 168:	07ce      	br      	0x104	// 104 <GPIO_Init+0x30>
        case 10:data_temp=0xfffff0ff;GPIO_Pin=8;break;
 16a:	3108      	movi      	r1, 8
 16c:	117b      	lrw      	r3, 0xfffff0ff	// 258 <GPIO_DriveStrength_DIS+0x8>
 16e:	07f5      	br      	0x158	// 158 <GPIO_Init+0x84>
        case 11:data_temp=0xffff0fff;GPIO_Pin=12;break;
 170:	310c      	movi      	r1, 12
 172:	117b      	lrw      	r3, 0xffff0fff	// 25c <GPIO_DriveStrength_DIS+0xc>
 174:	07f2      	br      	0x158	// 158 <GPIO_Init+0x84>
        case 12:data_temp=0xfff0ffff;GPIO_Pin=16;break;
 176:	3110      	movi      	r1, 16
 178:	117a      	lrw      	r3, 0xfff10000	// 260 <GPIO_DriveStrength_DIS+0x10>
        case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break;
 17a:	2b00      	subi      	r3, 1
 17c:	07ee      	br      	0x158	// 158 <GPIO_Init+0x84>
        case 13:data_temp=0xff0fffff;GPIO_Pin=20;break;
 17e:	3114      	movi      	r1, 20
 180:	1179      	lrw      	r3, 0xff100000	// 264 <GPIO_DriveStrength_DIS+0x14>
 182:	07fc      	br      	0x17a	// 17a <GPIO_Init+0xa6>
        case 14:data_temp=0xf0ffffff;GPIO_Pin=24;break;
 184:	33f1      	movi      	r3, 241
 186:	3118      	movi      	r1, 24
 188:	4378      	lsli      	r3, r3, 24
 18a:	07f8      	br      	0x17a	// 17a <GPIO_Init+0xa6>
        case 15:data_temp=0x0fffffff;GPIO_Pin=28;break;
 18c:	311c      	movi      	r1, 28
 18e:	1177      	lrw      	r3, 0xfffffff	// 268 <GPIO_DriveStrength_DIS+0x18>
 190:	07e4      	br      	0x158	// 158 <GPIO_Init+0x84>
        case 8:data_temp=0xfffffff0;GPIO_Pin=0;break;
 192:	3300      	movi      	r3, 0
 194:	3100      	movi      	r1, 0
 196:	2b0f      	subi      	r3, 16
 198:	07e0      	br      	0x158	// 158 <GPIO_Init+0x84>
         (GPIOx)->CONHR = ((GPIOx)->CONHR & data_temp) | 2<<GPIO_Pin;    
 19a:	3202      	movi      	r2, 2
 19c:	07e3      	br      	0x162	// 162 <GPIO_Init+0x8e>

0000019e <GPIO_Init2>:
//val=0x22222222 all IO as output
//ReturnValue:NONE
/*************************************************************/  
void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,uint32_t val)
{
    if (byte==0)
 19e:	3940      	cmpnei      	r1, 0
 1a0:	0803      	bt      	0x1a6	// 1a6 <GPIO_Init2+0x8>
    {
        (GPIOx)->CONLR=val;
 1a2:	b040      	st.w      	r2, (r0, 0)
    }
    else if(byte==1)
    {
        (GPIOx)->CONHR=val;
    }
}
 1a4:	783c      	rts
    else if(byte==1)
 1a6:	3941      	cmpnei      	r1, 1
 1a8:	0bfe      	bt      	0x1a4	// 1a4 <GPIO_Init2+0x6>
        (GPIOx)->CONHR=val;
 1aa:	b041      	st.w      	r2, (r0, 0x4)
}
 1ac:	07fc      	br      	0x1a4	// 1a4 <GPIO_Init2+0x6>

000001ae <GPIO_MODE_Init>:
//IO_MODE:IECR(IO INT ENABLE)
//IO_MODE:IGRP(IO INT GROUP)
//ReturnValue:NONE
/*************************************************************/  
void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,uint32_t val)
{
 1ae:	14d0      	push      	r15
        switch (IO_MODE)
 1b0:	3907      	cmphsi      	r1, 8
{
 1b2:	6cc3      	mov      	r3, r0
        switch (IO_MODE)
 1b4:	0809      	bt      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
 1b6:	6c07      	mov      	r0, r1
 1b8:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
 1bc:	0a080604 	.long	0x0a080604
 1c0:	14100e0c 	.long	0x14100e0c
        {
            case 0:(GPIOx)->PUDR  = val;break;               
 1c4:	b348      	st.w      	r2, (r3, 0x20)
			case 4:(GPIOx)->IEER  = val;break;
			case 5:(GPIOx)->IEDR  = val;break;
            case 6:EXIGRP->IGRPL  = val;break;
			case 7:EXIGRP->IGRPH  = val;break;
        }
}
 1c6:	1490      	pop      	r15
            case 1:(GPIOx)->DSCR  = val;break;
 1c8:	b349      	st.w      	r2, (r3, 0x24)
 1ca:	07fe      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
            case 2:(GPIOx)->OMCR  = val;break;
 1cc:	b34a      	st.w      	r2, (r3, 0x28)
 1ce:	07fc      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
            case 3:(GPIOx)->IECR  = val;break;
 1d0:	b34b      	st.w      	r2, (r3, 0x2c)
 1d2:	07fa      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
			case 4:(GPIOx)->IEER  = val;break;
 1d4:	b34c      	st.w      	r2, (r3, 0x30)
 1d6:	07f8      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
			case 5:(GPIOx)->IEDR  = val;break;
 1d8:	b34d      	st.w      	r2, (r3, 0x34)
 1da:	07f6      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
            case 6:EXIGRP->IGRPL  = val;break;
 1dc:	1164      	lrw      	r3, 0	// 26c <GPIO_DriveStrength_DIS+0x1c>
 1de:	9360      	ld.w      	r3, (r3, 0)
 1e0:	b340      	st.w      	r2, (r3, 0)
 1e2:	07f2      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>
			case 7:EXIGRP->IGRPH  = val;break;
 1e4:	1162      	lrw      	r3, 0	// 26c <GPIO_DriveStrength_DIS+0x1c>
 1e6:	9360      	ld.w      	r3, (r3, 0)
 1e8:	b341      	st.w      	r2, (r3, 0x4)
}
 1ea:	07ee      	br      	0x1c6	// 1c6 <GPIO_MODE_Init+0x18>

000001ec <GPIO_PullHigh_Init>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->PUDR  = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x01<<(bit*2));
 1ec:	4121      	lsli      	r1, r1, 1
 1ee:	3303      	movi      	r3, 3
 1f0:	70c4      	lsl      	r3, r1
 1f2:	9048      	ld.w      	r2, (r0, 0x20)
 1f4:	6cce      	nor      	r3, r3
 1f6:	68c8      	and      	r3, r2
 1f8:	3201      	movi      	r2, 1
 1fa:	7084      	lsl      	r2, r1
 1fc:	6cc8      	or      	r3, r2
 1fe:	b068      	st.w      	r3, (r0, 0x20)
}
 200:	783c      	rts

00000202 <GPIO_PullLow_Init>:
void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->PUDR  = (((GPIOx)->PUDR) & ~(0x03<<(bit*2))) | (0x02<<(bit*2));
 202:	4121      	lsli      	r1, r1, 1
 204:	3303      	movi      	r3, 3
 206:	70c4      	lsl      	r3, r1
 208:	9048      	ld.w      	r2, (r0, 0x20)
 20a:	6cce      	nor      	r3, r3
 20c:	68c8      	and      	r3, r2
 20e:	3202      	movi      	r2, 2
 210:	7084      	lsl      	r2, r1
 212:	6cc8      	or      	r3, r2
 214:	b068      	st.w      	r3, (r0, 0x20)
}
 216:	783c      	rts

00000218 <GPIO_PullHighLow_DIS>:
void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->PUDR  = ((GPIOx)->PUDR) & ~(0x03<<(bit*2));
 218:	4121      	lsli      	r1, r1, 1
 21a:	3303      	movi      	r3, 3
 21c:	70c4      	lsl      	r3, r1
 21e:	9048      	ld.w      	r2, (r0, 0x20)
 220:	6cce      	nor      	r3, r3
 222:	68c8      	and      	r3, r2
 224:	b068      	st.w      	r3, (r0, 0x20)
}
 226:	783c      	rts

00000228 <GPIO_OpenDrain_EN>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->OMCR  = ((GPIOx)->OMCR) | (0x01<<bit);
 228:	3301      	movi      	r3, 1
 22a:	904a      	ld.w      	r2, (r0, 0x28)
 22c:	70c4      	lsl      	r3, r1
 22e:	6cc8      	or      	r3, r2
 230:	b06a      	st.w      	r3, (r0, 0x28)
}
 232:	783c      	rts

00000234 <GPIO_OpenDrain_DIS>:
void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->OMCR  = ((GPIOx)->OMCR) & ~(0x01<<bit);
 234:	3300      	movi      	r3, 0
 236:	2b01      	subi      	r3, 2
 238:	904a      	ld.w      	r2, (r0, 0x28)
 23a:	70c7      	rotl      	r3, r1
 23c:	68c8      	and      	r3, r2
 23e:	b06a      	st.w      	r3, (r0, 0x28)
}
 240:	783c      	rts

00000242 <GPIO_DriveStrength_EN>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,U8_T bit)
{
	(GPIOx)->DSCR  = ((GPIOx)->DSCR) | (0x03<<(bit*2));
 242:	4121      	lsli      	r1, r1, 1
 244:	3303      	movi      	r3, 3
 246:	9049      	ld.w      	r2, (r0, 0x24)
 248:	70c4      	lsl      	r3, r1
 24a:	6cc8      	or      	r3, r2
 24c:	b069      	st.w      	r3, (r0, 0x24)
}
 24e:	783c      	rts

00000250 <GPIO_DriveStrength_DIS>:
void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,U8_T bit)
{
 250:	0410      	br      	0x270	// 270 <GPIO_DriveStrength_DIS+0x20>
 252:	0000      	bkpt
 254:	00000000 	.long	0x00000000
 258:	fffff0ff 	.long	0xfffff0ff
 25c:	ffff0fff 	.long	0xffff0fff
 260:	fff10000 	.long	0xfff10000
 264:	ff100000 	.long	0xff100000
 268:	0fffffff 	.long	0x0fffffff
 26c:	00000000 	.long	0x00000000
	(GPIOx)->DSCR  = ((GPIOx)->DSCR) & ~(0x03<<(bit*2));
 270:	4121      	lsli      	r1, r1, 1
 272:	3303      	movi      	r3, 3
 274:	70c4      	lsl      	r3, r1
 276:	9049      	ld.w      	r2, (r0, 0x24)
 278:	6cce      	nor      	r3, r3
 27a:	68c8      	and      	r3, r2
 27c:	b069      	st.w      	r3, (r0, 0x24)
}
 27e:	783c      	rts

00000280 <GPIO_IntGroup_Set>:
//EntryParameter:
//IO_MODE:IGRP(IO INT GROUP)
//ReturnValue:NONE
/*************************************************************/  
void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE)
{
 280:	14d0      	push      	r15
        switch (IO_MODE)
 282:	3804      	cmphsi      	r0, 5
 284:	080b      	bt      	0x29a	// 29a <GPIO_IntGroup_Set+0x1a>
 286:	1361      	lrw      	r3, 0	// 408 <GPIOA0_EXI_Init+0xf2>
        {
            case 0:EXIGRP->IGRPL  = 0X00000000;EXIGRP->IGRPH  = 0X00000000;break;               
            case 1:EXIGRP->IGRPL  = 0X11111111;EXIGRP->IGRPH  = 0X11111111;break;
            case 2:EXIGRP->IGRPL  = 0X22222222;EXIGRP->IGRPH  = 0X22222222;break;
            case 3:EXIGRP->IGRPL  = 0X33333333;EXIGRP->IGRPH  = 0X33333333;break;
			case 4:EXIGRP->IGRPL  = 0X44444444;EXIGRP->IGRPH  = 0X44444444;break;
 288:	9360      	ld.w      	r3, (r3, 0)
        switch (IO_MODE)
 28a:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
 28e:	0703      	.short	0x0703
 290:	000d0b09 	.long	0x000d0b09
            case 0:EXIGRP->IGRPL  = 0X00000000;EXIGRP->IGRPH  = 0X00000000;break;               
 294:	3200      	movi      	r2, 0
			case 4:EXIGRP->IGRPL  = 0X44444444;EXIGRP->IGRPH  = 0X44444444;break;
 296:	b340      	st.w      	r2, (r3, 0)
 298:	b341      	st.w      	r2, (r3, 0x4)
        }
}
 29a:	1490      	pop      	r15
            case 1:EXIGRP->IGRPL  = 0X11111111;EXIGRP->IGRPH  = 0X11111111;break;
 29c:	125c      	lrw      	r2, 0x11111111	// 40c <GPIOA0_EXI_Init+0xf6>
 29e:	07fc      	br      	0x296	// 296 <GPIO_IntGroup_Set+0x16>
            case 2:EXIGRP->IGRPL  = 0X22222222;EXIGRP->IGRPH  = 0X22222222;break;
 2a0:	125c      	lrw      	r2, 0x22222222	// 410 <GPIOA0_EXI_Init+0xfa>
 2a2:	07fa      	br      	0x296	// 296 <GPIO_IntGroup_Set+0x16>
            case 3:EXIGRP->IGRPL  = 0X33333333;EXIGRP->IGRPH  = 0X33333333;break;
 2a4:	125c      	lrw      	r2, 0x33333333	// 414 <GPIOA0_EXI_Init+0xfe>
 2a6:	07f8      	br      	0x296	// 296 <GPIO_IntGroup_Set+0x16>
			case 4:EXIGRP->IGRPL  = 0X44444444;EXIGRP->IGRPH  = 0X44444444;break;
 2a8:	125c      	lrw      	r2, 0x44444444	// 418 <GPIOA0_EXI_Init+0x102>
 2aa:	07f6      	br      	0x296	// 296 <GPIO_IntGroup_Set+0x16>

000002ac <GPIO_IntGroup_Set_1>:
//GPIOx:GPIOA0,GPIOA1,GPIOB0,GPIOC0,GPIOD0
//bit:0~15
//ReturnValue:NONE
/*************************************************************/  
void GPIO_IntGroup_Set_1(CSP_GPIO_T *GPIOx,U32_T bit)
{
 2ac:	14c1      	push      	r4
	U8_T Intbank =0;
	U8_T IntGroup = bit;
	U8_T maskshift;
	U32_T rwmask;
	switch((U32_T)GPIOx){
 2ae:	125c      	lrw      	r2, 0x40041000	// 41c <GPIOA0_EXI_Init+0x106>
 2b0:	6482      	cmpne      	r0, r2
	U8_T IntGroup = bit;
 2b2:	74c4      	zextb      	r3, r1
	switch((U32_T)GPIOx){
 2b4:	0c20      	bf      	0x2f4	// 2f4 <GPIO_IntGroup_Set_1+0x48>
 2b6:	6408      	cmphs      	r2, r0
 2b8:	0c06      	bf      	0x2c4	// 2c4 <GPIO_IntGroup_Set_1+0x18>
 2ba:	125a      	lrw      	r2, 0x40040100	// 420 <GPIOA0_EXI_Init+0x10a>
 2bc:	6482      	cmpne      	r0, r2
 2be:	0c0b      	bf      	0x2d4	// 2d4 <GPIO_IntGroup_Set_1+0x28>
	U8_T Intbank =0;
 2c0:	3200      	movi      	r2, 0
 2c2:	040a      	br      	0x2d6	// 2d6 <GPIO_IntGroup_Set_1+0x2a>
	switch((U32_T)GPIOx){
 2c4:	1258      	lrw      	r2, 0x40042000	// 424 <GPIOA0_EXI_Init+0x10e>
 2c6:	6482      	cmpne      	r0, r2
 2c8:	0c18      	bf      	0x2f8	// 2f8 <GPIO_IntGroup_Set_1+0x4c>
 2ca:	1258      	lrw      	r2, 0x40043000	// 428 <GPIOA0_EXI_Init+0x112>
 2cc:	6482      	cmpne      	r0, r2
 2ce:	0bf9      	bt      	0x2c0	// 2c0 <GPIO_IntGroup_Set_1+0x14>
		break;
		case APB_GPIOC0Base:
			Intbank = 3;
		break;
		case APB_GPIOD0Base:
			Intbank = 4;
 2d0:	3204      	movi      	r2, 4
		break;
 2d2:	0402      	br      	0x2d6	// 2d6 <GPIO_IntGroup_Set_1+0x2a>
			Intbank = 1;
 2d4:	3201      	movi      	r2, 1
		default:
		break;
	}		
	if(bit < 8){
 2d6:	3907      	cmphsi      	r1, 8
 2d8:	120c      	lrw      	r0, 0	// 408 <GPIOA0_EXI_Init+0xf2>
 2da:	0811      	bt      	0x2fc	// 2fc <GPIO_IntGroup_Set_1+0x50>
		maskshift = IntGroup<<2 ;
 2dc:	4362      	lsli      	r3, r3, 2
		rwmask = ~(0xF << maskshift);
 2de:	744c      	zextb      	r1, r3
 2e0:	330f      	movi      	r3, 15
		EXIGRP ->IGRPL = ((EXIGRP ->IGRPL) & rwmask) | (Intbank << maskshift);
 2e2:	9000      	ld.w      	r0, (r0, 0)
		rwmask = ~(0xF << maskshift);
 2e4:	70c4      	lsl      	r3, r1
		EXIGRP ->IGRPL = ((EXIGRP ->IGRPL) & rwmask) | (Intbank << maskshift);
 2e6:	9080      	ld.w      	r4, (r0, 0)
		rwmask = ~(0xF << maskshift);
 2e8:	6cce      	nor      	r3, r3
		EXIGRP ->IGRPL = ((EXIGRP ->IGRPL) & rwmask) | (Intbank << maskshift);
 2ea:	68d0      	and      	r3, r4
 2ec:	7084      	lsl      	r2, r1
 2ee:	6c8c      	or      	r2, r3
 2f0:	b040      	st.w      	r2, (r0, 0)
	else{
		maskshift = (IntGroup-8)<<2 ;
		rwmask = ~(0xF << maskshift);
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
	}		
}
 2f2:	1481      	pop      	r4
			Intbank = 2;
 2f4:	3202      	movi      	r2, 2
		break;
 2f6:	07f0      	br      	0x2d6	// 2d6 <GPIO_IntGroup_Set_1+0x2a>
			Intbank = 3;
 2f8:	3203      	movi      	r2, 3
		break;
 2fa:	07ee      	br      	0x2d6	// 2d6 <GPIO_IntGroup_Set_1+0x2a>
		maskshift = (IntGroup-8)<<2 ;
 2fc:	2b07      	subi      	r3, 8
 2fe:	4362      	lsli      	r3, r3, 2
		rwmask = ~(0xF << maskshift);
 300:	74cc      	zextb      	r3, r3
 302:	310f      	movi      	r1, 15
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
 304:	9000      	ld.w      	r0, (r0, 0)
		rwmask = ~(0xF << maskshift);
 306:	704c      	lsl      	r1, r3
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
 308:	9081      	ld.w      	r4, (r0, 0x4)
		rwmask = ~(0xF << maskshift);
 30a:	6c46      	nor      	r1, r1
		EXIGRP ->IGRPH = ((EXIGRP ->IGRPH) & rwmask) | (Intbank << maskshift);
 30c:	6850      	and      	r1, r4
 30e:	708c      	lsl      	r2, r3
 310:	6c84      	or      	r2, r1
 312:	b041      	st.w      	r2, (r0, 0x4)
}
 314:	07ef      	br      	0x2f2	// 2f2 <GPIO_IntGroup_Set_1+0x46>

00000316 <GPIOA0_EXI_Init>:
//IO EXI SET 
//EntryParameter:EXI_IO(EXI0~EXI13)
//ReturnValue:NONE
/*************************************************************/  
void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
 316:	14d0      	push      	r15
    switch (EXI_IO)
 318:	380f      	cmphsi      	r0, 16
 31a:	0812      	bt      	0x33e	// 33e <GPIOA0_EXI_Init+0x28>
 31c:	1264      	lrw      	r3, 0	// 42c <GPIOA0_EXI_Init+0x116>
 31e:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
 322:	0f08      	.short	0x0f08
 324:	2b241d15 	.long	0x2b241d15
 328:	463f3932 	.long	0x463f3932
 32c:	625b544c 	.long	0x625b544c
 330:	6e69      	.short	0x6e69
    {
        case 0:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
 332:	9340      	ld.w      	r2, (r3, 0)
 334:	9260      	ld.w      	r3, (r2, 0)
 336:	310f      	movi      	r1, 15
 338:	68c5      	andn      	r3, r1
 33a:	3ba0      	bseti      	r3, r3, 0
        case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 33c:	b260      	st.w      	r3, (r2, 0)
        case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break;
        case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break;
		case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X00100000;break;
		case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0X00100000;break;
    }
}
 33e:	1490      	pop      	r15
        case 1:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 340:	9340      	ld.w      	r2, (r3, 0)
 342:	9260      	ld.w      	r3, (r2, 0)
 344:	31f0      	movi      	r1, 240
 346:	68c5      	andn      	r3, r1
 348:	3ba4      	bseti      	r3, r3, 4
 34a:	07f9      	br      	0x33c	// 33c <GPIOA0_EXI_Init+0x26>
        case 2:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
 34c:	9320      	ld.w      	r1, (r3, 0)
 34e:	32f0      	movi      	r2, 240
 350:	9160      	ld.w      	r3, (r1, 0)
 352:	4244      	lsli      	r2, r2, 4
 354:	68c9      	andn      	r3, r2
 356:	3ba8      	bseti      	r3, r3, 8
        case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break;
 358:	b160      	st.w      	r3, (r1, 0)
 35a:	07f2      	br      	0x33e	// 33e <GPIOA0_EXI_Init+0x28>
        case 3:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
 35c:	9320      	ld.w      	r1, (r3, 0)
 35e:	32f0      	movi      	r2, 240
 360:	9160      	ld.w      	r3, (r1, 0)
 362:	4248      	lsli      	r2, r2, 8
 364:	68c9      	andn      	r3, r2
 366:	3bac      	bseti      	r3, r3, 12
 368:	07f8      	br      	0x358	// 358 <GPIOA0_EXI_Init+0x42>
        case 4:GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
 36a:	9320      	ld.w      	r1, (r3, 0)
 36c:	32f0      	movi      	r2, 240
 36e:	9160      	ld.w      	r3, (r1, 0)
 370:	424c      	lsli      	r2, r2, 12
 372:	68c9      	andn      	r3, r2
 374:	3bb0      	bseti      	r3, r3, 16
 376:	07f1      	br      	0x358	// 358 <GPIOA0_EXI_Init+0x42>
        case 5:GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
 378:	9320      	ld.w      	r1, (r3, 0)
 37a:	32f0      	movi      	r2, 240
 37c:	9160      	ld.w      	r3, (r1, 0)
 37e:	4250      	lsli      	r2, r2, 16
 380:	68c9      	andn      	r3, r2
 382:	3bb4      	bseti      	r3, r3, 20
 384:	07ea      	br      	0x358	// 358 <GPIOA0_EXI_Init+0x42>
        case 6:GPIOA0->CONLR = (GPIOA0->CONLR&0XF0FFFFFF) | 0X01000000;break;
 386:	9320      	ld.w      	r1, (r3, 0)
 388:	32f0      	movi      	r2, 240
 38a:	9160      	ld.w      	r3, (r1, 0)
 38c:	4254      	lsli      	r2, r2, 20
 38e:	68c9      	andn      	r3, r2
 390:	3bb8      	bseti      	r3, r3, 24
 392:	07e3      	br      	0x358	// 358 <GPIOA0_EXI_Init+0x42>
        case 7:GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF) | 0X10000000;break;
 394:	9340      	ld.w      	r2, (r3, 0)
 396:	9260      	ld.w      	r3, (r2, 0)
 398:	4364      	lsli      	r3, r3, 4
 39a:	4b64      	lsri      	r3, r3, 4
 39c:	3bbc      	bseti      	r3, r3, 28
 39e:	07cf      	br      	0x33c	// 33c <GPIOA0_EXI_Init+0x26>
        case 8:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0) | 0X00000001;break;
 3a0:	9340      	ld.w      	r2, (r3, 0)
 3a2:	9261      	ld.w      	r3, (r2, 0x4)
 3a4:	310f      	movi      	r1, 15
 3a6:	68c5      	andn      	r3, r1
 3a8:	3ba0      	bseti      	r3, r3, 0
		case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0X00100000;break;
 3aa:	b261      	st.w      	r3, (r2, 0x4)
}
 3ac:	07c9      	br      	0x33e	// 33e <GPIOA0_EXI_Init+0x28>
        case 9:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F) | 0X00000010;break;
 3ae:	9340      	ld.w      	r2, (r3, 0)
 3b0:	9261      	ld.w      	r3, (r2, 0x4)
 3b2:	31f0      	movi      	r1, 240
 3b4:	68c5      	andn      	r3, r1
 3b6:	3ba4      	bseti      	r3, r3, 4
 3b8:	07f9      	br      	0x3aa	// 3aa <GPIOA0_EXI_Init+0x94>
        case 10:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF) | 0X00000100;break;
 3ba:	9320      	ld.w      	r1, (r3, 0)
 3bc:	32f0      	movi      	r2, 240
 3be:	9161      	ld.w      	r3, (r1, 0x4)
 3c0:	4244      	lsli      	r2, r2, 4
 3c2:	68c9      	andn      	r3, r2
 3c4:	3ba8      	bseti      	r3, r3, 8
		case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X00100000;break;
 3c6:	b161      	st.w      	r3, (r1, 0x4)
 3c8:	07bb      	br      	0x33e	// 33e <GPIOA0_EXI_Init+0x28>
        case 11:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF) | 0X00001000;break;
 3ca:	9320      	ld.w      	r1, (r3, 0)
 3cc:	32f0      	movi      	r2, 240
 3ce:	9161      	ld.w      	r3, (r1, 0x4)
 3d0:	4248      	lsli      	r2, r2, 8
 3d2:	68c9      	andn      	r3, r2
 3d4:	3bac      	bseti      	r3, r3, 12
 3d6:	07f8      	br      	0x3c6	// 3c6 <GPIOA0_EXI_Init+0xb0>
        case 12:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF) | 0X00010000;break;
 3d8:	9320      	ld.w      	r1, (r3, 0)
 3da:	32f0      	movi      	r2, 240
 3dc:	9161      	ld.w      	r3, (r1, 0x4)
 3de:	424c      	lsli      	r2, r2, 12
 3e0:	68c9      	andn      	r3, r2
 3e2:	3bb0      	bseti      	r3, r3, 16
 3e4:	07f1      	br      	0x3c6	// 3c6 <GPIOA0_EXI_Init+0xb0>
        case 13:GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF) | 0X00100000;break;
 3e6:	9320      	ld.w      	r1, (r3, 0)
 3e8:	32f0      	movi      	r2, 240
 3ea:	9161      	ld.w      	r3, (r1, 0x4)
 3ec:	4250      	lsli      	r2, r2, 16
		case 14:GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF) | 0X00100000;break;
 3ee:	68c9      	andn      	r3, r2
 3f0:	3bb4      	bseti      	r3, r3, 20
 3f2:	07ea      	br      	0x3c6	// 3c6 <GPIOA0_EXI_Init+0xb0>
 3f4:	9320      	ld.w      	r1, (r3, 0)
 3f6:	32f1      	movi      	r2, 241
 3f8:	9161      	ld.w      	r3, (r1, 0x4)
 3fa:	4254      	lsli      	r2, r2, 20
 3fc:	07f9      	br      	0x3ee	// 3ee <GPIOA0_EXI_Init+0xd8>
		case 15:GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFFF) | 0X00100000;break;
 3fe:	9340      	ld.w      	r2, (r3, 0)
 400:	9261      	ld.w      	r3, (r2, 0x4)
 402:	3bb4      	bseti      	r3, r3, 20
 404:	07d3      	br      	0x3aa	// 3aa <GPIOA0_EXI_Init+0x94>
 406:	0000      	bkpt
 408:	00000000 	.long	0x00000000
 40c:	11111111 	.long	0x11111111
 410:	22222222 	.long	0x22222222
 414:	33333333 	.long	0x33333333
 418:	44444444 	.long	0x44444444
 41c:	40041000 	.long	0x40041000
 420:	40040100 	.long	0x40040100
 424:	40042000 	.long	0x40042000
 428:	40043000 	.long	0x40043000
 42c:	00000000 	.long	0x00000000

00000430 <GPIOA1_EXI_Init>:
void GPIOA1_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
 430:	14d0      	push      	r15
    switch (EXI_IO)
 432:	3805      	cmphsi      	r0, 6
 434:	080f      	bt      	0x452	// 452 <GPIOA1_EXI_Init+0x22>
 436:	1274      	lrw      	r3, 0	// 584 <GPIOA00_Set_ResetPin+0x14>
 438:	1254      	lrw      	r2, 0	// 588 <GPIOA00_Set_ResetPin+0x18>
        case 0:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
        case 1:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
        case 2:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
        case 3:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
        case 4:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
        case 5:GPIOA1->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
 43a:	9360      	ld.w      	r3, (r3, 0)
 43c:	9220      	ld.w      	r1, (r2, 0)
 43e:	9360      	ld.w      	r3, (r3, 0)
    switch (EXI_IO)
 440:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
 444:	110c0803 	.long	0x110c0803
 448:	1b16      	.short	0x1b16
        case 0:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFFF0) | 0X00000001;break;
 44a:	320f      	movi      	r2, 15
 44c:	68c9      	andn      	r3, r2
 44e:	3ba0      	bseti      	r3, r3, 0
        case 5:GPIOA1->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
 450:	b160      	st.w      	r3, (r1, 0)
		default:break;
    }
}
 452:	1490      	pop      	r15
        case 1:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 454:	32f0      	movi      	r2, 240
 456:	68c9      	andn      	r3, r2
 458:	3ba4      	bseti      	r3, r3, 4
 45a:	07fb      	br      	0x450	// 450 <GPIOA1_EXI_Init+0x20>
        case 2:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFFF0FF) | 0X00000100;break;
 45c:	32f0      	movi      	r2, 240
 45e:	4244      	lsli      	r2, r2, 4
 460:	68c9      	andn      	r3, r2
 462:	3ba8      	bseti      	r3, r3, 8
 464:	07f6      	br      	0x450	// 450 <GPIOA1_EXI_Init+0x20>
        case 3:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFFF0FFF) | 0X00001000;break;
 466:	32f0      	movi      	r2, 240
 468:	4248      	lsli      	r2, r2, 8
 46a:	68c9      	andn      	r3, r2
 46c:	3bac      	bseti      	r3, r3, 12
 46e:	07f1      	br      	0x450	// 450 <GPIOA1_EXI_Init+0x20>
        case 4:GPIOA1->CONLR = (GPIOA0->CONLR&0XFFF0FFFF) | 0X00010000;break;
 470:	32f0      	movi      	r2, 240
 472:	424c      	lsli      	r2, r2, 12
 474:	68c9      	andn      	r3, r2
 476:	3bb0      	bseti      	r3, r3, 16
 478:	07ec      	br      	0x450	// 450 <GPIOA1_EXI_Init+0x20>
        case 5:GPIOA1->CONLR = (GPIOA0->CONLR&0XFF0FFFFF) | 0X00100000;break;
 47a:	32f0      	movi      	r2, 240
 47c:	4250      	lsli      	r2, r2, 16
 47e:	68c9      	andn      	r3, r2
 480:	3bb4      	bseti      	r3, r3, 20
 482:	07e7      	br      	0x450	// 450 <GPIOA1_EXI_Init+0x20>

00000484 <GPIOB0_EXI_Init>:
void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
    switch (EXI_IO)
 484:	3840      	cmpnei      	r0, 0
 486:	0c04      	bf      	0x48e	// 48e <GPIOB0_EXI_Init+0xa>
 488:	3841      	cmpnei      	r0, 1
 48a:	0c0a      	bf      	0x49e	// 49e <GPIOB0_EXI_Init+0x1a>
    {
        case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break;
        case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
        default:break;
    }
}
 48c:	783c      	rts
        case 0:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0) | 0X00000001;break;
 48e:	1260      	lrw      	r3, 0	// 58c <GPIOA00_Set_ResetPin+0x1c>
 490:	310f      	movi      	r1, 15
 492:	9340      	ld.w      	r2, (r3, 0)
 494:	9260      	ld.w      	r3, (r2, 0)
 496:	68c5      	andn      	r3, r1
 498:	3ba0      	bseti      	r3, r3, 0
        case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 49a:	b260      	st.w      	r3, (r2, 0)
}
 49c:	07f8      	br      	0x48c	// 48c <GPIOB0_EXI_Init+0x8>
        case 1:GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 49e:	117c      	lrw      	r3, 0	// 58c <GPIOA00_Set_ResetPin+0x1c>
 4a0:	31f0      	movi      	r1, 240
 4a2:	9340      	ld.w      	r2, (r3, 0)
 4a4:	9260      	ld.w      	r3, (r2, 0)
 4a6:	68c5      	andn      	r3, r1
 4a8:	3ba4      	bseti      	r3, r3, 4
 4aa:	07f8      	br      	0x49a	// 49a <GPIOB0_EXI_Init+0x16>

000004ac <GPIOC0_EXI_Init>:
void GPIOC0_EXI_Init(GPIO_EXI_TypeDef EXI_IO)
{
 4ac:	14d0      	push      	r15
    switch (EXI_IO)
 4ae:	3803      	cmphsi      	r0, 4
 4b0:	080c      	bt      	0x4c8	// 4c8 <GPIOC0_EXI_Init+0x1c>
 4b2:	1178      	lrw      	r3, 0	// 590 <GPIOA00_Set_ResetPin+0x20>
 4b4:	e0000000 	bsr      	0	// 0 <___gnu_csky_case_uqi>
 4b8:	170f0902 	.long	0x170f0902
    {
        case 0:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFFF0) | 0X00000001;break;
 4bc:	9340      	ld.w      	r2, (r3, 0)
 4be:	9260      	ld.w      	r3, (r2, 0)
 4c0:	310f      	movi      	r1, 15
 4c2:	68c5      	andn      	r3, r1
 4c4:	3ba0      	bseti      	r3, r3, 0
        case 1:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 4c6:	b260      	st.w      	r3, (r2, 0)
        case 2:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFF0FF) | 0X00000100;break;
        case 3:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFF0FFF) | 0X00001000;break;
        default:break;
    }
}
 4c8:	1490      	pop      	r15
        case 1:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFFF0F) | 0X00000010;break;
 4ca:	9340      	ld.w      	r2, (r3, 0)
 4cc:	9260      	ld.w      	r3, (r2, 0)
 4ce:	31f0      	movi      	r1, 240
 4d0:	68c5      	andn      	r3, r1
 4d2:	3ba4      	bseti      	r3, r3, 4
 4d4:	07f9      	br      	0x4c6	// 4c6 <GPIOC0_EXI_Init+0x1a>
        case 2:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFFF0FF) | 0X00000100;break;
 4d6:	9320      	ld.w      	r1, (r3, 0)
 4d8:	32f0      	movi      	r2, 240
 4da:	9160      	ld.w      	r3, (r1, 0)
 4dc:	4244      	lsli      	r2, r2, 4
 4de:	68c9      	andn      	r3, r2
 4e0:	3ba8      	bseti      	r3, r3, 8
        case 3:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFF0FFF) | 0X00001000;break;
 4e2:	b160      	st.w      	r3, (r1, 0)
}
 4e4:	07f2      	br      	0x4c8	// 4c8 <GPIOC0_EXI_Init+0x1c>
        case 3:GPIOC0->CONLR = (GPIOC0->CONLR&0XFFFF0FFF) | 0X00001000;break;
 4e6:	9320      	ld.w      	r1, (r3, 0)
 4e8:	32f0      	movi      	r2, 240
 4ea:	9160      	ld.w      	r3, (r1, 0)
 4ec:	4248      	lsli      	r2, r2, 8
 4ee:	68c9      	andn      	r3, r2
 4f0:	3bac      	bseti      	r3, r3, 12
 4f2:	07f8      	br      	0x4e2	// 4e2 <GPIOC0_EXI_Init+0x36>

000004f4 <GPIO_EXI_EN>:
void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
    (GPIOx)->IECR  |= 1<<EXI_IO;
 4f4:	3301      	movi      	r3, 1
 4f6:	904b      	ld.w      	r2, (r0, 0x2c)
 4f8:	70c4      	lsl      	r3, r1
 4fa:	6cc8      	or      	r3, r2
 4fc:	b06b      	st.w      	r3, (r0, 0x2c)
}
 4fe:	783c      	rts

00000500 <GPIO_EXI_ENSet>:
void GPIO_EXI_ENSet(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
    (GPIOx)->IEER  |= 1<<EXI_IO;
 500:	3301      	movi      	r3, 1
 502:	904c      	ld.w      	r2, (r0, 0x30)
 504:	70c4      	lsl      	r3, r1
 506:	6cc8      	or      	r3, r2
 508:	b06c      	st.w      	r3, (r0, 0x30)
}
 50a:	783c      	rts

0000050c <GPIO_EXI_DISSet>:
void GPIO_EXI_DISSet(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO)
{
    (GPIOx)->IEDR  |= 1<<EXI_IO;
 50c:	3301      	movi      	r3, 1
 50e:	904d      	ld.w      	r2, (r0, 0x34)
 510:	70c4      	lsl      	r3, r1
 512:	6cc8      	or      	r3, r2
 514:	b06d      	st.w      	r3, (r0, 0x34)
}
 516:	783c      	rts

00000518 <GPIO_Write_High>:
//bit:0~15
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Write_High(CSP_GPIO_T *GPIOx,U8_T bit)
{
        (GPIOx)->SODR = (1ul<<bit);
 518:	3301      	movi      	r3, 1
 51a:	70c4      	lsl      	r3, r1
 51c:	b063      	st.w      	r3, (r0, 0xc)
}
 51e:	783c      	rts

00000520 <GPIO_Write_Low>:
void GPIO_Write_Low(CSP_GPIO_T *GPIOx,U8_T bit)
{
        (GPIOx)->CODR = (1ul<<bit);
 520:	3301      	movi      	r3, 1
 522:	70c4      	lsl      	r3, r1
 524:	b064      	st.w      	r3, (r0, 0x10)
}
 526:	783c      	rts

00000528 <GPIO_Set_Value>:
//bitposi:0~15 bitval:0~1 0=low 1=high
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Set_Value(CSP_GPIO_T *GPIOx,U8_T bitposi,U8_T bitval)
{
    if (bitval==1)
 528:	3a41      	cmpnei      	r2, 1
 52a:	0804      	bt      	0x532	// 532 <GPIO_Set_Value+0xa>
    {
        (GPIOx)->SODR = (1ul<<bitposi);
 52c:	7084      	lsl      	r2, r1
 52e:	b043      	st.w      	r2, (r0, 0xc)
    }
    else if ((bitval==0))
    {
        (GPIOx)->CODR = (1ul<<bitposi);
    }
}
 530:	783c      	rts
    else if ((bitval==0))
 532:	3a40      	cmpnei      	r2, 0
 534:	0bfe      	bt      	0x530	// 530 <GPIO_Set_Value+0x8>
        (GPIOx)->CODR = (1ul<<bitposi);
 536:	3301      	movi      	r3, 1
 538:	70c4      	lsl      	r3, r1
 53a:	b064      	st.w      	r3, (r0, 0x10)
}
 53c:	07fa      	br      	0x530	// 530 <GPIO_Set_Value+0x8>

0000053e <GPIO_Reverse>:
//ReturnValue:VALUE
/*************************************************************/
void GPIO_Reverse(CSP_GPIO_T *GPIOx,U8_T bit)
{
     uint32_t dat = 0;
     dat=((GPIOx)->ODSR>>bit)&1ul;
 53e:	9045      	ld.w      	r2, (r0, 0x14)
 540:	3301      	movi      	r3, 1
 542:	7085      	lsr      	r2, r1
 544:	688c      	and      	r2, r3
     {
       if (dat==1)  
 546:	3a40      	cmpnei      	r2, 0
 548:	70c4      	lsl      	r3, r1
 54a:	0c03      	bf      	0x550	// 550 <GPIO_Reverse+0x12>
       {
           (GPIOx)->CODR = (1ul<<bit);
 54c:	b064      	st.w      	r3, (r0, 0x10)
       {
           (GPIOx)->SODR = (1ul<<bit);
           return;
       }
     }
}
 54e:	783c      	rts
           (GPIOx)->SODR = (1ul<<bit);
 550:	b063      	st.w      	r3, (r0, 0xc)
           return;
 552:	07fe      	br      	0x54e	// 54e <GPIO_Reverse+0x10>

00000554 <GPIO_Read_Status>:
/*************************************************************/
uint8_t GPIO_Read_Status(CSP_GPIO_T *GPIOx,U8_T bit)
{
    uint8_t value = 0;
    uint32_t dat = 0;
    dat=((GPIOx)->PSDR)&(1<<bit);
 554:	3301      	movi      	r3, 1
 556:	9046      	ld.w      	r2, (r0, 0x18)
 558:	70c4      	lsl      	r3, r1
 55a:	688c      	and      	r2, r3
    if (dat == (1<<bit))								
 55c:	64ca      	cmpne      	r2, r3
	{
	    value = 1;
	} 
    return value;
 55e:	6403      	mvcv      	r0
}
 560:	783c      	rts

00000562 <GPIO_Read_Output>:
/*************************************************************/
uint8_t GPIO_Read_Output(CSP_GPIO_T *GPIOx,U8_T bit)
{
    uint8_t value = 0;
    uint32_t dat = 0;
    dat=((GPIOx)->ODSR)&(1<<bit);
 562:	3301      	movi      	r3, 1
 564:	9045      	ld.w      	r2, (r0, 0x14)
 566:	70c4      	lsl      	r3, r1
 568:	688c      	and      	r2, r3
    if (dat == (1<<bit))								
 56a:	64ca      	cmpne      	r2, r3
	{
	    value = 1;
	} 
    return value;
 56c:	6403      	mvcv      	r0
}
 56e:	783c      	rts

00000570 <GPIOA00_Set_ResetPin>:
//EntryParameter:NONE
//ReturnValue:VALUE
/*************************************************************/
void GPIOA00_Set_ResetPin()
{
    GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006; 
 570:	1065      	lrw      	r3, 0	// 584 <GPIOA00_Set_ResetPin+0x14>
 572:	310f      	movi      	r1, 15
 574:	9340      	ld.w      	r2, (r3, 0)
 576:	9260      	ld.w      	r3, (r2, 0)
 578:	68c5      	andn      	r3, r1
 57a:	3ba1      	bseti      	r3, r3, 1
 57c:	3ba2      	bseti      	r3, r3, 2
 57e:	b260      	st.w      	r3, (r2, 0)
}
 580:	783c      	rts
	...
